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rev 1.1 data sheet no. pd60304 IRMCF341 sensorless motor control ic for appliances features ? mce tm (motion control engine) - hardware based computation engine for high efficiency sinusoidal sensorless control of permanent magnet ac motor ? supports both interior and surface permanent magnet motors ? built-in hardware peripheral for single shunt current feedback reconstruction ? no external current or voltage sensing operational amplifier required ? three/two-phase space vector pwm ? three-channel analog output (pwm) ? embedded 8-bit high speed microcontroller (8051) for flexible i/o and man-machine control ? jtag programming port for emulation/debugger ? serial communication interface (uart) ? i 2 c/spi serial interface ? watchdog timer with independent analog clock ? three general purpose timers/counters ? two special timers: periodi c timer, capture timer ? external eeprom and internal ram facilitate debugging and code development ? pin compatible with irmck341, otp-rom version ? 1.8v/3.3v cmos product summary maximum crystal frequency 60 mhz maximum internal clock (sysclk) frequency 128 mhz sensorless control computation time 11 sec typ mce tm computation data range 16 bit signed program ram loaded from external eeprom 48k bytes data ram 8k bytes gatekill latency (digital filtered) 2 sec pwm carrier frequency counter 16 bits/ sysclk a/d input channels 8 a/d converter resolution 12 bits a/d converter conversion speed 2 sec 8051 instruction execution speed 2 sysclk analog output (pwm) resolution 8 bits uart baud rate (typ) 57.6k bps number of i/o (max) 24 package (lead-free) qfp64 description IRMCF341 is a high performance ram based motion control ic designed primarily for appliance applications. IRMCF341 is designed to achieve low cost and high per formance control solutions for advanced inverterized appliance motor control. IRMCF341 contains two computation engi nes. one is motion control engine (mce tm ) for sensorless control of permanent magnet motors; the other is an 8-bit hi gh-speed microcontroller (8051). both com putation engines are integrated into one monolithic chip. the mce tm contains a collection of control elements such as proportional plus integral, vector rotator, angle estimator, multiply/divide, low loss svpwm, single shunt ifb. t he user can program a moti on control algorithm by connecting these control elements using a graphic compiler. key components of the sensorless control algor ithms, such as the angle estimator, are provided as comple te pre-defined control blocks implemented in hardware. a unique analog/digital circuit and algorithm to fully support single shunt current reconstruction is also provided. the 8051 microcontroller performs 2-cycle instruction execution (60mi ps at 120mhz). the mce and 8051 microcontroller are connected via dual port ram to process signal monitoring and command input. an advanced graphic compiler for the mce tm is seamlessly integrated into the matlab/simulink environment, while third party jtag based em ulator tools are supported for 8051 developments. IRMCF341 comes with a small qfp64 pin lead-free package.
IRMCF341 2 table of contents 1 overview ..................................................................................................................... ............... 4 2 IRMCF341 block diagram and main functions......................................................................... 5 3 pinout....................................................................................................................... .................. 7 4 input/output of IRMCF341..................................................................................................... .... 8 4.1 8051 peripheral interface group ......................................................................................... 8 4.2 motion peripheral interface group .................................................................................... 10 4.3 analog interface group ..................................................................................................... 10 4.4 power interface group ...................................................................................................... 11 4.5 test interface group ....................................................................................................... .. 11 5 application connections ...................................................................................................... .... 12 6 dc characteristics ........................................................................................................... ........ 13 6.1 absolute maximum ratings............................................................................................... 13 6.2 system clock frequency and power consumption .......................................................... 13 6.3 digital i/o dc characteristics............................................................................................ 14 6.4 pll and oscillator dc characteristics............................................................................... 15 6.5 analog i/o dc characteristics .......................................................................................... 15 6.6 under voltage lockout dc characteristics........................................................................ 16 6.7 cmext and aref characteristics ................................................................................... 16 7 ac characteristics ........................................................................................................... ........ 17 7.1 pll ac characteristics ..................................................................................................... 17 7.2 analog to digital converter ac characteristics................................................................. 18 7.3 op amp ac characteristics............................................................................................... 19 7.4 sync to svpwm and a/d conversion ac timing ........................................................... 20 7.5 gatekill to svpwm ac timing ..................................................................................... 21 7.6 interrupt ac timing ........................................................................................................ ... 21 7.7 i 2 c ac timing.................................................................................................................... 22 7.8 spi ac timing.............................................................................................................. ..... 23 7.8.1 spi write ac timing .................................................................................................... 23 7.8.2 spi read ac timing................................................................................................... 24 7.9 uart ac timing............................................................................................................. .. 25 7.10 capture input ac timing ........................................................................................... 26 7.11 jtag ac timing ............................................................................................................ 27 8 pin list ..................................................................................................................... ................ 28 9 package dimensions ........................................................................................................... .... 31 10 part marking information .................................................................................................... .. 32
IRMCF341 3 table of figures figure 1. typical application block diagram using IRMCF341..................................................... 4 figure 2. IRMCF341 internal block diagram ................................................................................. 5 figure 3. IRMCF341 pin configuration.......................................................................................... 7 figure 4. input/output of IRMCF341............................................................................................ .. 8 figure 5. application connection of IRMCF341 .......................................................................... 12 figure 6. clock frequency vs. power consumption.................................................................... 13 table of tables table 1. absolute maximum ratings ........................................................................................... 13 table 2. system clock frequency ............................................................................................... 13 table 3. digital i/o dc characteristics ....................................................................................... . 14 table 4. pll dc characteristics ............................................................................................... .. 15 table 5. analog i/o dc characteristics ....................................................................................... 15 table 6. uvcc dc characteristics .............................................................................................. . 16 table 7. cmext and aref dc characteristics.......................................................................... 16 table 8. pll ac characteristics............................................................................................... ... 17 table 9. a/d converter ac characteristics ................................................................................. 18 table 10. current sensing op amp ac characteristics.............................................................. 19 table 11. sync ac characteristics ............................................................................................ 20 table 12. gatekill to svpwm ac timing ............................................................................... 21 table 13. interrupt ac timing................................................................................................. ..... 21 table 14. i 2 c ac timing .............................................................................................................. 22 table 15. spi write ac timing ................................................................................................. ... 23 table 16. spi read ac timing.................................................................................................. .. 24 table 17. uart ac timing ...................................................................................................... ... 25 table 18. capture ac timing .................................................................................................. 26 table 19. jtag ac timing ...................................................................................................... .... 27 table 20. pin list ............................................................................................................ ............. 30
IRMCF341 4 1 overview IRMCF341 is a new international rectifier int egrated circuit device primarily designed as a one- chip solution for complete inverter controlled appliance motor control applications. unlike a traditional microcontroller or dsp, the IRMCF341 provides a built-in closed loop sensorless control algorithm using the unique motion control engine (mce tm ) for permanent magnet motors. the mce tm consists of a collection of control elements, motion peripherals, a dedicated motion control sequencer and dual port ram to map internal signal nodes. IRMCF341 also employs a unique single shunt current reconstruction circuit to eliminate additional analog/digital circuitry and enables a direct shunt resistor interface to the ic. motion control programming is achieved using a dedicated graphical compiler integrated into the matlab/simulink tm development environment. sequencing, user interface, host communication, and upper layer control tasks can be implemented in the 8051 high-speed 8-bit microcontroller. the 8051 microcontroller is equipped with a jtag port to facilitate emulation and debugging tools. figure 1 shows a typical application schematic using the IRMCF341. IRMCF341 is intended for development purpose and contains 48k bytes of ram, which can be loaded from external eeprom for 8051 program execution. for high volume production, irmck341 contains otp rom in place of program ram to reduce the cost. both IRMCF341 and irmck341 come in the same 64-pin qfp package with identical pin configuration to facilitate pc board layout and transition to mass production IRMCF341 multiple output power supply hvic gate drive & protection circuit upto 24 digital input/output i 2 c interface to eeprom 7 analog input appliance inverter 3.3 v 1.8 v passive emi filter uart interface to front panel motor (pmsm) figure 1. typical application block diagram using IRMCF341
IRMCF341 5 2 IRMCF341 block diagram and main functions IRMCF341 block diagram is shown in figure 2. 8bit up address/data bus motion control bus figure 2. IRMCF341 internal block diagram IRMCF341 contains the following functions for sensorless ac motor control applications: ? motion control engine (mce tm ) o proportional plus integral block o low pass filter o differentiator and lag (high pass filter) o ramp o limit o angle estimate (sensorless control) o inverse clark transformation o vector rotator o bit latch o peak detect
IRMCF341 6 o transition o multiply-divide (signed and unsigned) o divide (signed and unsigned) o adder o subtractor o comparator o counter o accumulator o switch o shift o atan (arc tangent) o function block (any curve fitting, nonlinear function) o 16-bit wide logic operations (and, or, xor, not, negate) o mce tm program and data memory (6k byte). note 1 o mce tm control sequencer ? 8051 microcontroller o three 16-bit timer/counters o 16-bit periodic timer o 16-bit analog watchdog timer o 16-bit capture timer o up to 24 discrete i/os o eight-channel 12-bit a/d ? one buffered channel for current sensing (0 ? 1.2v input) ? seven unbuffered channels (0 ? 1.2v input) o jtag port (4 pins) o up to three channels of analog output (8-bit pwm) o uart o i 2 c/spi port o 48k byte program ram loaded from external eeprom o 2k byte data ram. note 1 note 1: total size of ram is 8k byte including mce program, mce data, and 8051 data. different sizes can be allocated depending on applications.
IRMCF341 7 3 pinout figure 3. IRMCF341 pin configuration
IRMCF341 8 4 input/output of IRMCF341 all i/o signals of IRMCF341 are shown in figure 4. all i/o pins are 3.3v logic interface except a/d interface pins. pwmuh pwmul pwmvh pwmvl pwmwh pwmwl gatekill ifb+ ifb- ifbo ain0 ain1 pwm gate signal interface a/d interface discrete i/o jtag port uart interface xtal0 xtal1 crystal d/a interface (pwm output) reset system reset ain2 ain3 avdd (1.8v) avss cmext vdd1 (3.3v) vdd2 (1.8v) vss digital power/ ground tstmod test mode (must be tied to vss) pllvdd (1.8v) pllvss pll power/ ground p1.2/txd p1.1/rxd sda/cs0 scl/so-si p1.4/cap p1.0/t2 p1.5 p1.6 p1.7 p2.0/nmi p1.3/sync/sck p3.0/int2/cs1 p2.1 p2.2 p2.3 p2.4 p2.5 p3.2/int0 p3.3/int1 p3.5/t1 i2c interface p5.3/tdi tck p5.1/tms p5.2/tdo p2.6/aopwm0 p2.7/aopwm1 p3.1/aopwm2 ain4 ain5 ain6 aref analog power/ ground figure 4. input/output of IRMCF341 4.1 8051 peripheral interface group uart interface txd output, transmit data from IRMCF341 rxd input, receive data to IRMCF341 discrete i/o interface p1.0/t2 input/output port 1.0, can be configured as timer/counter 2 input p1.1/rxd input/output port 1.1, can be configured as rxd input p1.2/txd input/output port 1.2, can be configured as txd output
IRMCF341 9 p1.3/sync/sck input/output port 1.3, can be configured as sync output or spi clock output, needs to be pulled up to vdd1 in order to boot from i 2 c eeprom p1.4/cap input/output port 1.4, can be configured as capture timer input p1.5 input/output port 1.5 p1.6 input/output port 1.6 p1.7 input/output port 1.7 p2.0/nmi input/output port 2.0, can be configured as non-maskable interrupt input p2.1 input/output port 2.1 p2.2 input/output port 2.2 p2.3 input/output port 2.3 p2.4 input/output port 2.4 p2.5 input/output port 2.5 p2.6/aopwm0 input/output port 2.6, can be configured as aopwm0 output p2.7/aopwm1 input/output port 2.7, can be configured as aopwm1 output p3.0/int2/cs1 input/output port 3.0, can be configured as int2 input or spi chip select 1 p3.1/aopwm2 input/output port 3.1, can be configured as aopwm2 output p3.2/nint0 input/output port 3.2, can be configured as int0 input p3.3/nint1 input/output port 3.3, can be configured as int1 input p3.5/t1 input/output port 3.5, can be configured as timer/counter 1 input p5.1/tsm input/output port 5.1, configured as jtag port by default p5.2/tdo input/output port 5.2, configured as jtag port by default p5.3/tdi input/output port 5.3, configured as jtag port by default analog output interface p2.6/aopwm0 input/output, can be configured as 8-bit pwm output 0 with programmable carrier frequency p2.7/aopwm1 input/output, can be configured as 8-bit pwm output 1 with programmable carrier frequency p3.1/aopwm2 input/output, can be configured as 8-bit pwm output 2 with programmable carrier frequency crystal interface xtal0 input, connected to crystal xtal1 output, connected to crystal reset interface reset inout, system reset, needs to be pulled up to vdd1 but doesn?t require external rc time constant i 2 c interface scl/so-si output, i 2 c clock output, or spi data sda/cs0 input/output, i 2 c data line or spi chip select 0 i 2 c/spi interface scl/so-si output, i 2 c clock output, or spi data sda/cs0 input/output, i 2 c data line or spi chip select 0
IRMCF341 10 p1.3/sync/sck input/output port 1.3, can be configured as sync output or spi clock output, needs to be pulled up to vdd1 in order to boot from i 2 c eeprom p3.0/int2/cs1 input/output port 3.0, can be configured as int2 input or spi chip select 1 4.2 motion peripheral interface group pwm pwmuh output, pwm phase u high side gate signal pwmul output, pwm phase u low side gate signal pwmvh output, pwm phase v high side gate signal pwmvl output, pwm phase v low side gate signal pwmwh output, pwm phase w high side gate signal pwmwl output, pwm phase w low side gate signal fault gatekill input, upon assertion, this negates all six pwm signals, programmable logic sense 4.3 analog interface group avdd analog power (1.8v) avss analog power return aref 0.6v buffered output cmext unbuffered 0.6v, input to the aref buffer, capacitor needs to be connected. ifb+ input, operational amplifier positive input for shunt resistor current sensing ifb- input, operational amplifier negative input for shunt resistor current sensing ifbo output, operational amplifier output for shunt resistor current sensing ain0 input, analog input channel 0 (0 ? 1.2v), typically configured for dc bus voltage input ain1 input, analog input channel 1 (0 ? 1.2v), needs to be pulled down to avss if unused ain2 input, analog input channel 2 (0 ? 1.2v), needs to be pulled down to avss if unused ain3 input, analog input channel 3 (0 ? 1.2v), needs to be pulled down to avss if unused ain4 input, analog input channel 4 (0 ? 1.2v), needs to be pulled down to avss if unused ain5 input, analog input channel 5 (0 ? 1.2v), needs to be pulled down to avss if unused ain6 input, analog input channel 6 (0 ? 1.2v), needs to be pulled down to avss if unused
IRMCF341 11 4.4 power interface group vdd1 digital power for i/o (3.3v) vdd2 digital power for core logic (1.8v) vss digital common pllvdd pll power (1.8v) pllvss pll ground return 4.5 test interface group tstmod must be tied to vss, used only for factory testing. p5.1/tsm input/output port 5.1, configured as jtag port by default p5.2/tdo input/output port 5.2, configured as jtag port by default p5.3/tdi input/output port 5.3, configured as jtag port by default tck input, jtag test clock
IRMCF341 12 5 application connections typical application connection is shown in figure 5. all components necessary to implement a complete sensorless drive control algorithm are shown connected to IRMCF341. figure 5. application connection of IRMCF341
IRMCF341 13 6 dc characteristics 6.1 absolute maximum ratings symbol parameter min typ max condition v dd1 supply voltage -0.3 v - 3.6 v respect to vss v dd2 supply voltage -0.3 v - 1.98 v respect to vss v ia analog input voltage -0.3 v - 1.98 v respect to avss v id digital input voltage -0.3 v - 3.65 v respect to vss t a ambient temperature -40 ? c - 85 ? c t s storage temperature -65 ? c - 150 ? c table 1. absolute maximum ratings caution: stresses beyond those listed in ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. 6.2 system clock frequency and power consumption symbol parameter min typ max unit sysclk system clock 32 - 128 mhz table 2. system clock frequency figure 6. clock frequency vs. power consumption 0 40 80 120 160 200 240 0 50 100 150 clock frequency (mhz) power (mw) vdd2 (1.8v) vdd1 (3.3v) total
IRMCF341 14 6.3 digital i/o dc characteristics symbol parameter min typ max condition v dd1 supply voltage 3.0 v 3.3 v 3.6 v recommended v dd2 supply voltage 1.62 v 1.8 v 1.98 v recommended v il input low voltage -0.3 v - 0.8 v recommended v ih input high voltage 2.0 v 3.6 v recommended c in input capacitance - 3.6 pf - (1) i l input leakage current 10 na 1 a v o = 3.3 v or 0 v i ol1 (2) low level output current 8.9 ma 13.2 ma 15.2 ma v ol = 0.4 v (1) i oh1 (2) high level output current 12.4 ma 24.8 ma 38 ma v oh = 2.4 v (1) i ol2 (3) low level output current 17.9 ma 26.3 ma 33.4 ma v ol = 0.4 v (1) i oh2 (3) high level output current 24.6 ma 49.5 ma 81 ma v oh = 2.4 v (1) table 3. digital i/o dc characteristics note: (1) data guaranteed by design. (2) applied to scl/so-si, sda/cs0 pins. (3) applied to p1.0/t2, p1.1/rxd, p1.2/txd, p1.3/sync/sck, p1.4/cap, p1.5, p1.6, p1.7, p2.0/nmi, p2.1, p2.2, p2.3, p2.4, p2.5, p2.6/aopwm0, p2.7/aopwm1, p3.0/int2/cs1, p3.1/aopwm2, p3.2/int0, p3.3/int1, p3.5/t1, p3.6/rxd1, p3.7/txd1, p5.1/tms, p5.2/tdo, p5.3/tdi, gatekill, pwmul, pwmuh, pwmvl, pwmvh, pwmwl, and pwmwh pins.
IRMCF341 15 6.4 pll and oscillator dc characteristics symbol parameter min typ max condition v pllvdd supply voltage 1.62 v 1.8 v 1.92 v recommended v il osc oscillator input low voltage v pllvss - 0.2* v pllvdd v pllvdd = 1.8 v (1) v ih osc oscillator input high voltage 0.8* v pllvdd v pllvdd v pllvdd = 1.8 v (1) table 4. pll dc characteristics note: (1) data guaranteed by design. 6.5 analog i/o dc characteristics - op amp for current sensing (ifb+, ifb-, ifbo) c aref = 1nf, c mext = 100nf. unless specified, ta = 25 ? c. symbol parameter min typ max condition v avdd supply voltage 1.71 v 1.8 v 1.89 v recommended v offset input offset voltage - - 26 mv v avdd = 1.8 v v i input voltage range 0 v 1.2 v recommended v outsw op amp output operating range 50 mv (1) - 1.2 v v avdd = 1.8 v c in input capacitance - 3.6 pf - (1) r fdbk op amp feedback resistor 5 k - 20 k requested between ifbo and ifb- op gaincl operating close loop gain 80 db - - (1) cmrr common mode rejection ratio - 80 db - (1) i src op amp output source current - 1 ma - v out = 0.6 v (1) i snk op amp output sink current - 100 a - v out = 0.6 v (1) table 5. analog i/o dc characteristics note: (1) data guaranteed by design.
IRMCF341 16 6.6 under voltage lockout dc characteristics - based on avdd (1.8v) unless specified, ta = 25 ? c. symbol parameter min typ max condition uv cc+ uvcc positive going threshold 1.53 v 1.66 v 1.71 v v dd1 = 3.3 v uv cc- uvcc negative going threshold 1.52 v 1.62 v 1.71 v v dd1 = 3.3 v uv cc h uvcc hysteresys - 40 mv - table 6. uvcc dc characteristics 6.7 cmext and aref characteristics c aref = 1nf, c mext = 100nf. unless specified, ta = 25 ? c. symbol parameter min typ max condition v cm cmext voltage 495 mv 600 mv 700 mv v avdd = 1.8 v v aref buffer output voltage 495 mv 600 mv 700 mv v avdd = 1.8 v v o load regulation (v dc -0.6) - 1 mv - (1) psrr power supply rejection ratio - 75 db - (1) table 7. cmext and aref dc characteristics
IRMCF341 17 7 ac characteristics 7.1 pll ac characteristics symbol parameter min typ max condition f clkin crystal input frequency 3.2 mhz 4 mhz 60 mhz (1) (see figure below) f pll internal clock frequency 32 mhz 50 mhz 128 mhz (1) f lwpw sleep mode output frequency f clkin 256 - - (1) j s short time jitter - 200 psec - (1) d duty cycle - 50 % - (1) t lock pll lock time - - 500 sec (1) table 8. pll ac characteristics note: (1) data guaranteed by design. xtal r 1 =1m r 2 =10 c 1 =30pf c 2 =30pf
IRMCF341 18 7.2 analog to digital converter ac characteristics unless specified, ta = 25 ? c. symbol parameter min typ max condition t conv conversion time - - 2.05 sec (1) t hold sample/hold maximum hold time - - 10 sec voltage droop 15 lsb (see figure below) table 9. a/d converter ac characteristics note: (1) data guaranteed by design. t hold voltage droop t sample s/h voltage input voltage
IRMCF341 19 7.3 op amp ac characteristics - op amp for current sensing (ifb+, ifb-, ifbo) unless specified, ta = 25 ? c. symbol parameter min typ max condition op sr op amp slew rate - 10 v/ sec - v avdd = 1.8 v, cl = 33 pf (1) op imp op input impedance - 10 8 ? - (1) t set settling time - 400 ns - v avdd = 1.8 v, cl = 33 pf (1) table 10. current sensing op amp ac characteristics note: (1) data guaranteed by design.
IRMCF341 20 7.4 sync to svpwm and a/d conversion ac timing sync iu,iv,iw t wsync t dsync1 ainx t dsync2 pwmux,pwmvx,pwmwx t dsync3 unless specified, ta = 25 ? c. symbol parameter min typ max unit t wsync sync pulse width - 32 - sysclk t dsync1 sync to current feedback conversion time - - 100 sysclk t dsync2 sync to ain0-6 analog input conversion time - - 200 sysclk (1) t dsync3 sync to pwm output delay time - - 2 sysclk table 11. sync ac characteristics note: (1) ain1 through ain6 channels are converted once every 6 sync events
IRMCF341 21 7.5 gatekill to svpwm ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t wgk gatekill pulse width 32 - - sysclk t dgk gatekill to pwm output delay - - 100 sysclk table 12. gatekill to svpwm ac timing 7.6 interrupt ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t wint int0, int1 interrupt assertion time 4 - - sysclk t dint int0, int1 latency - - 4 sysclk table 13. interrupt ac timing
IRMCF341 22 7.7 i 2 c ac timing scl sda t i2st1 t i2st2 t i2wsetup t i2clk t i2whold t i2rsetup t i2rhold t i2clk t i2en1 t i2en2 unless specified, ta = 25 ? c. symbol parameter min typ max unit t i2clk i 2 c clock period 10 - 8192 sysclk t i2st1 i 2 c sda start time 0.25 - - t i2clk t i2st2 i 2 c scl start time 0.25 - - t i2clk t i2wsetup i 2 c write setup time 0.25 - - t i2clk t i2whold i 2 c write hold time 0.25 - - t i2clk t i2rsetup i 2 c read setup time i 2 c filter time (1) - - sysclk t i2rhold i 2 c read hold time 1 - - sysclk table 14. i 2 c ac timing note: (1) i 2 c read setup time is determined by the programmable filter time applied to i 2 c communication.
IRMCF341 23 7.8 spi ac timing 7.8.1 spi write ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t spiclk spi clock period 4 - - sysclk t spiclkht spi clock high time - 1/2 - t spiclk t spiclklt spi clock low time - 1/2 - t spiclk t csdelay cs to data delay time - - 10 nsec t wrdelay clk falling edge to data delay time - - 10 nsec t cshigh cs high time between two consecutive byte transfer 1 - - t spiclk t cshold cs hold time - 1 - t spiclk table 15. spi write ac timing
IRMCF341 24 7.8.2 spi read ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t spiclk spi clock period 4 - - sysclk t spiclkht spi clock high time - 1/2 - t spiclk t spiclklt spi clock low time - 1/2 - t spiclk t csrd cs to data delay time - - 10 nsec t rdsu spi read data setup time 10 - - nsec t rdhold spi read data hold time 10 - - nsec t cshigh cs high time between two consecutive byte transfer 1 - - t spiclk t cshold cs hold time - 1 - t spiclk table 16. spi read ac timing
IRMCF341 25 7.9 uart ac timing txd rxd data and parity bit start bit t baud stop bit t uartfil unless specified, ta = 25 ? c. symbol parameter min typ max unit t baud baud rate period - 57600 - bit/sec t uartfil uart sampling filter period (1) - 1/16 - t baud table 17. uart ac timing note: (1) each bit including start and stop bit is sampled three times at center of a bit at an interval of 1/16 t baud . if three sampled values do not agree, then uart noise error is generated.
IRMCF341 26 7.10 capture input ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t capclk capture input period 8 - - sysclk t caphigh capture input high time 4 - - sysclk t caplow capture input low time 4 - - sysclk t crdelay capture falling edge to capture register latch time - - 4 sysclk t cldelay capture rising edge to capture register latch time - - 4 sysclk t intdelay capture input interrupt latency time - - 4 sysclk table 18. capture ac timing
IRMCF341 27 7.11 jtag ac timing tck tdo t jhigh t jclk t co t jlow t jsetup t jhold tdi/tms unless specified, ta = 25 ? c. symbol parameter min typ max unit t jclk tck period - - 50 mhz t jhigh tck high period 10 - - nsec t jlow tck low period 10 - - nsec t co tck to tdo propagation delay time 0 - 5 nsec t jsetup tdi/tms setup time 4 - - nsec t jhold tdi/tms hold time 0 - - nsec table 19. jtag ac timing
IRMCF341 28 8 pin list pin number pin name internal pull-up /pull-down pin type description 1 xtal0 i crystal input 2 xtal1 o crystal output 3 p1.0/t2 i/o discrete programmable i/o or timer/counter 2 input 4 p1.1/rxd i/o discrete programmable i/o or uart receive input 5 p1.2/txd i/o discrete programmable i/o or uart transmit output 6 p1.3/sync/sck i/o discrete programmable i/o or sync output or spi clock output, needs to be pulled up to vdd1 in order to boot from i 2 c eeprom 7 p1.4/cap i/o discrete programmable i/o or capture timer input 8 p1.5 i/o discrete programmable i/o 9 p1.6 i/o discrete programmable i/o 10 p1.7 i/o discrete programmable i/o 11 vdd2 p 1.8v digital power 12 vss p digital common 13 vdd1 p 3.3v digital power 14 p2.0/nmi i/o discrete programmable i/o or non-maskable interrupt input 15 p2.1 i/o discrete programmable i/o 16 p2.2 i/o discrete programmable i/o 17 p2.3 i/o discrete programmable i/o 18 p2.4 i/o discrete programmable i/o 19 p2.5 i/o discrete programmable i/o 20 p2.6/aopwm0 i/o discrete programmable i/o or pwm 0 digital output 21 p2.7/aopwm1 i/o discrete programmable i/o or pwm 1 digital output 22 vdd2 p 1.8v digital power 23 vss p digital common 24 ain0 i analog input channel 0, 0-1.2v range, needs to be pulled down to avss if unused 25 avdd p 1.8v analog power 26 avss p analog common 27 ain1 i analog input channel 1, 0-1.2v range, needs to be pulled down to avss if unused 28 cmext o unbuffered 0.6v output. capacitor needs to be connected. 29 aref o analog reference voltage output (0.6v) 30 ifb- i single shunt current sensing op amp input (-) 31 ifb+ i single shunt current sensing op amp input (+) 32 ifbo o single shunt current sensing op amp output
IRMCF341 29 pin number pin name internal pull-up /pull-down pin type description 33 ain2 i analog input channel 2, 0-1.2v range, needs to be pulled down to avss if unused 34 ain3 i analog input channel 3, 0-1.2v range, needs to be pulled down to avss if unused 35 ain4 i analog input channel 4, 0-1.2v range, needs to be pulled down to avss if unused 36 ain5 i analog input channel 5, 0-1.2v range, needs to be pulled down to avss if unused 37 ain6 i analog input channel 6, 0-1.2v range, needs to be pulled down to avss if unused 38 vdd2 p 1.8v digital power 39 vss p digital common 40 vdd1 p 3.3v digital power 41 gatekill i pwm shutdown input, 2- sec digital filter, configurable either high or low true. 42 pwmwl 70 k ? pull up o pwm gate drive for phase w low side, configurable either high or low true 43 pwmwh 70 k ? pull up o pwm gate drive for phase w high side, configurable either high or low true 44 pwmvl 70 k ? pull up o pwm gate drive for phase v low side, configurable either high or low true 45 pwmvh 70 k ? pull up o pwm gate drive for phase v high side, configurable either high or low true 46 pwmul 70 k ? pull up o pwm gate drive for phase u low side, configurable either high or low true 47 pwmuh 70 k ? pull up o pwm gate drive for phase u high side, configurable either high or low true 48 p3.0/int2/cs1 i/o discrete programmable i/o or external interrupt 2 input or spi chip select 1 49 p3.1/aopwm2 i/o discrete programmable i/o or pwm 2 digital output 50 p3.2/int0 i/o discrete programmable i/o or interrupt 0 input 51 p3.3/int1 i/o discrete programmable i/o or interrupt 1 input 52 p3.5/t1 i/o discrete programmable i/o or timer/counter 1 53 vss p digital common 54 vdd1 p 3.3v digital power 55 scl/so-si i/o i 2 c clock output (open drain, need pull up) or spi data 56 sda/cs0 i/o i 2 c data (open drain, need pull up) or spi chip select 0 57 p5.1/tms i/o jtag test mode select 58 p5.2/tdo i/o jtag test data output 59 p5.3/tdi i/o jtag test data input 60 tck i jtag test clock
IRMCF341 30 pin number pin name internal pull-up /pull-down pin type description 61 tstmod 58 k ? pull down i test mode. must be tied to vss. factory use only 62 reset i/o reset, low true, schmitt trigger input 63 pllvdd p 1.8v pll power 64 pllvss p pll ground table 20. pin list
IRMCF341 31 9 package dimensions
IRMCF341 32 10 part marking information IRMCF341 ywwp xxxxxx ir logo production lot date code part number pin 1 indentifier order information lead-free part in 64-lead qfp moisture sensitivity rating ? msl3 part number order quantities IRMCF341tr 1500 parts on tape and reel in dry pack IRMCF341ty 1600 parts on trays (160 parts per tray) in dry pack the lqfp-64 is msl3 qualified this product has been designed and qualified for the industrial level qualification standards can be found at www.irf.com ir world headquarters: 233 kansas st., el segundo, california 90245, tel: (310) 252-7105 data and specifications subject to change wi thout notic e. 12/05/2006 www.irf.com

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